1. Field of the Invention
This invention is related to the field of integrated circuits and, more particularly, memories included in integrated circuits.
2. Description of the Related Art
As the size of various transistor features continue to be reduced from generation to generation of semiconductor manufacturing processes, issues related to the aging of transistors increase in importance. Typically, the effects of aging over a defined lifetime for an integrated circuit (e.g. 5 years) are accounted for by adding additional margin into the supply voltage required to power the integrated circuit (increasing the magnitude of the supply voltage above the minimum at which the integrated circuit could theoretically operate).
One such aging effect is negative bias temperature instability (NBTI). NBTI primarily affects P-type metal-oxide-semiconductor (PMOS) transistors, and causes the threshold voltage of the transistors to increase in magnitude over time. The transistors thus turn on more slowly in response to changes in gate to source voltage, slowing down overall operation of the circuit.
NBTI is of particular concern in the memory array cells. The memory array cells include PMOS transistors, one of which is active at a given point in time retaining a binary one (VDD voltage level) on one of the two nodes of the memory array cell (either the true or complement node in the memory cell). In order to provide reliable storage, the cells are designed to be symmetrical. If symmetry is lost, reliability in the cell decreases. If NBTI effects to the PMOS transistors in the cell are unequal, the symmetry of the memory cell can be lost. Early failure of the integrated circuit can result.